Comprehensive mobility study of silicon nanowire transistors using multi-subband models

Spatial confinement is important in advanced More Moore devices, such as nanowire transistors (NWTs), where the basic charge transport properties must be revised beyond the bulk crystal assumptions. This work presents a comprehensive and general overview of the electron mobility in aggressively-scaled SiNWTs in order to demonstrate the effect of quantum confinement on this topic, establishing its dependence on numerous physical factors (shape, diameter, and orientation). The mobility evaluation makes use of a unique simulation framework and innovative multi-subband calculations of the scattering rates.Weshow that (1) the effect of surface roughness scattering is more pronounced at higher sheet densities, (2) ionized impurity scattering seriously degrades the mobility in highly-doped NWTs, and (3) the cross-section shape affects directly the subband parameters and the mobility, with the ellipticalNWTsgiving the best performance for the same cross-sectional area.European Unionʼs Horizon 2020 research and innovation programme under grant agreement No 688 101 SUPERAID7Incorporación Fellowship scheme under grant agreement No. IJC2019-040003-I (MICINN/AEI

Statistical device simulations of III-V nanowire resonant tunneling diodes as physical unclonable functions source

In this paper, utilising the non-equilibrium Green’s function (NEGF) formalism within the new device simulator NESS (Nano-Electronic Software Simulator) developed at the University of Glasgow’s Device Modelling Group, we present quantum mechanical simulations of current flow in double-barrier III-V GaAs-AlGaAs nanowire resonant tunneling diodes (RTDs). NESS is a fast and modular Technology Computer Aided Design (TCAD) tool with flexible architecture which can take into account various sources of statistical variability in nanodevices. The aim of this work is to show that, in the RTD devices with nano-scale dimensions, there is a direct correlation between the position and the numbers of random dopants and the key device parameters, e.g., position of the resonant-peak (VR) variations as well as the shape and number of peaks in the output current–voltage (I-V) characteristics. Such VR variability can be used as a quantum fingerprint which can provide robust security and hence can be used to deliver Physical Unclonable Functions (PUFs).UK Research & Innovation (UKRI) Engineering & Physical Sciences Research Council (EPSRC) EP/S001131/1 EP/P009972/

Confinement orientation effects in S/D tunneling

The most extensive research of scaled electronic devices involves the inclusion of quantum effects in the transport direction as transistor dimensions approach nanometer scales. Moreover, it is necessary to study how these mechanisms affect different transistor architectures to determine which one can be the best candidate to implement future nodes. This work implements Source-to-Drain Tunneling mechanism (S/D tunneling) in a Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator showing the modification in the distribution of the electrons in the subbands, and, consequently, in the potential profile due to different confinement direction between DGSOIs and FinFETs.Spanish Ministry of Science and Innovation (TEC2014-59730-R), H2020 - REMINDER (687931), and H2020 - WAYTOGO-FAST (662175

Impact of non uniform strain configuration on transport properties for FD14+ devices

As device dimensions are scaled down, the use of non-geometrical performance boosters becomes of special relevance. In this sense, strained channels are proposed for the 14 nm FDSOI node. However this option may introduce a new source of variability since strain distribution inside the channel is not uniform at such scales. In this work, a MS-EMC study of different strain configurations including non-uniformities is presented showing drain current degradation because of the increase of intervalley phonon scattering and the subsequent variations of transport effective mass and drift velocity. This effect, which has an intrinsic statistical origin, will make necessary further optimizations to keep the expected boosting capabilities of strained channels

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called NanoElectronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a driftdiffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.European Union Horizon 2020 - 688101 SUPERAID7EPSRC UKRI Innovation Fellowship - EP/S001131/1 (QSEE), No. EP/P009972/1 (QUANTDEVMOD)H2020-FETOPEN-2019 s- No.862539-Electromed-FET OPEN.No. EP/S000259/1(Variability PDK for design based research on FPGA/neuro computing

Full-band quantum transport simulation in presence of hole-phonon interactions using a mode-space k·p approach

Fabrication techniques at the nanometer scale offer potential opportunities to access single dopant features in nanoscale transistors. Here we report full-band quantum transport simulations with hole-phonon interactions through a device consisting of two gates- all-around in series and a p-type Si nanowire channel with a single-dopant within each gated region. For this purpose, we have developed and implemented a mode-space based full-band quantum transport simulator with phonon scattering using the six-band k.p method. Based on the non-equilibrium Green's function formalism and the self-consistent Born's approximation, an expression for the hole-phonon interactions self-energy within the mode-space representation is introduced

DFT-based layered dielectric model of few-layer MoS2

The authors would like to thank the financial support of projects H2020-MSCA-IF-2019 Ref. 895322 (EU Horizon 2020 programme), TEC2017-89800-R (Spanish State Research Agency, AEI), P18-RT-4826 (Regional Government of Andalusia) and B-TIC-515-UGR18 (University of Granada). Funding for open access charge: Universidad de Granada/ CBUA.We employ atomistic calculations to study charge distribution in few-layer MoS2 structures with an applied perpendicular electric field. The results suggest a simple continuum model consisting of alternating regions which represent the semiconductor layers and the Van der Waals gaps between them. Such model is a first step towards an accurate simulation of MoS2 in TCAD tools.H2020-MSCA-IF-2019 Ref. 895322 (EU Horizon 2020 programme)TEC2017-89800-R (Spanish State Research Agency, AEI)P18-RT-4826 (Regional Government of Andalusia)B-TIC-515-UGR18 (University of Granada)Funding for open access charge: Universidad de Granada/ CBU

Implementation of Band-to-Band Tunneling Phenomena in a Multisubband Ensemble Monte Carlo Simulator: Application to Silicon TFETs

TFETs are in the way to become an alternative to conventional MOSFETs due to the possibility of achieving low subthreshold swing (SS) combined with small OFF current levels which allows operation at low VDD. In this work, a non-local band–to–band tunneling (BTBT) model has been successfully implemented into a Multi-Subband Ensemble Monte Carlo (MSEMC) simulator and applied to ultra-scaled silicon-based n-type TFETs. We have considered two different criteria for the choice of the tunneling path followed by the carriers when crossing the potential barrier, which leads to different distributions of the generated electron-hole pairs. Subband discretization due to field–induced quantum confinement has been taken into account. TCAD simulations accounting for quantization effects are considered for comparison purposes providing very accurate agreement with MS-EMC results

Impact of the Trap Attributes on the Gate Leakage Mechanisms in a 2D MS-EMC Nanodevice Simulator

From a modeling point of view, the inclusion of adequate physical phenomena is mandatory when analyzing the behavior of new transistor architectures. In particular, the high electric field across the ultra-thin insulator in aggressively scaled transistors leads to the possibility for the charge carriers in the channel to tunnel through the gate oxide via various gate leakage mechanisms (GLMs). In this work, we study the impact of trap number on gate leakage using the GLM model, which is included in a Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator for Fully-Depleted Silicon-On-Insulator (FDSOI) field effect transistors (FETs). The GLM code described herein considers both direct and trap-assisted tunneling. This work shows that trap attributes and dynamics can modify the device electrostatic characteristics and even play a significant role in determining the extent of GLMs.The research leading to these results has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 688101 SUPERAID7

Assessment of Pseudo-Bilayer Structures in the Heterogate Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistor

We investigate the effect of pseudo-bilayer configurations at low operating voltages (<0.5V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of the inversion layer for electrons. Resulting benefits from this setup are: improved electrostatic control on the channel, enhanced gate-to-gate efficiency and higher Ion levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures